Coincident current core memory fabrication



US. Cl. 340174 United States Patent 3,495,226 COINCIDENT CURRENT CORE MEMORY FABRICATION Klaus J. Boelmke, Kelkheim, Taunus, Germany, assignor to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Filed Mar. 3, 1966, Ser. No. 531,595 Int. Cl. Gllb 5/00 1 Claim ABSTRACT OF THE DISCLOSURE The present device provides a multi-plane memory mounted on a single plane. The cores are arranged in N rows and M columns wherein N is the number of bits in a digit and M is a multiple of the number of digits in a word. The magnetizable cores are so arranged that row driver lines can be fitted vertically through M columns of cores without any complicated threading procedures. Likewise, the column driver lines can be fitted vertically through selected columns of cores with as many column lines as there are digits in a word. Further the bit driver line and the sense amplifier line are threaded horizontally through a row of cores with one of each for each row of cores. Finally the cores are so arranged that in conjunction with the wiring arrangement the pulses received by the sense amplifier are of a single polarity.

This invention relates to data storage devices, and more particularly, to the fabrication of coincident current magnetizable core memories. This invention and application is the property of the Sperry Rand Corporation.

The use of coincident current core memories in data processing systems is well known. Such memories are usually made up of a plurality of magnetizable cores, each of which is capable of being magnetized in first and second states of magnetization. The magnetizable cores are divided into a plurality of groups. Each of said groups is designated as belonging to a plane. Heretofore the magnetizable cores of each plane have been arranged in a matrix by rows and columns and the counterpart cores in each plane are considered together as making up a digit. In other words, the individual cores which are located at the row 1, column 1 positions of the respective planes are considered together as making up a digit. The digit has the number of bits therein which is equal to the number of planes. In addition, in the prior art, the cores have electrically conductive wires threaded therethrough with the wires defining the rows and the columns.

In coincident current memories a row Wire and a column wire are selected and electrically energized. Accordingly, all of the cores which lie along the selected row wire on a plane and all the cores which lie along the selected column wire on a plane are subjected to the magnetic flux which is generated by the electrical current passing respectively along these selected row and column wires. It is necessary to provide a discrete amount of flux to cause a core to change from said first magnetic state to said second magnetic state.

It is the practice, in coincident current memories, to generate this discrete amount of flux at a selected core by providing two signals (electrical currents) thereat each of which is one-half of the electrical current necessary to generate the discrete amount of flux. The flux gen- 3,495,226 Patented Feb. 10, 1970 erated, respectively, by the two one-half current signals is additive and hence this combined flux is equal to the discrete amount of flux which is necessary to switch the selected core from one state of magnetization to the other. However, in accordance with this practice each of the cores, in addition to the selected core, which lies along a row wire is subjected to the one-half current signal and in like manner each of the cores, in addition to the selected core, which lies along the selected column wire is also subjected to the one-half current signal. Accordingly, these additional row and column cores are partially switched and generate a small signal which is identified as noise.

It has been found that in reasonably large core memories the addition of the half noise is sufiiciently large that it interferes with the system discrimination between a bona fide information signal and the noise. Accordingly, it is the practice to arrange the cores and the sens ing wire such that the sensing Wire passes through approximately half of the cores in one direction and through the other half in a second direction. In one direction the sense line enters through a face of the core which lies opposite from the face of the core into which the roW and column wires pass and in the second direction the sense line enters the face of the core into which the row and column passes. By arranging the sense wire in such a fashion the noise signals generated by approximately half the cores cancels out the noise signals generated by the other half of the cores. In order to effect this last arrangement it is necessary to thread the sense line on a bias; that is, instead of having the sense line pass along either a row or a column it is disposed to pass diagonally across the core array and intersect consecutively the cores from many different rows and many different columns.

In order to fabricate sucha core memory it is a somewhat costly operation to thread the sense line or the sense wire diagonally through the cores. Further, it has been found that since the cores are arranged to have the noise generated in one-half the cores in opposition to the noise generated in the other half of the cores, there occurs the situation that the particular selected core may generate either a positive or a negative output signal.

The present invention provides a fabrication arrangement whereby the sense line in each plane is simply threaded along what appears to be a row position since the whole plane is arranged to lie along a row. Further, in accordance with the present invention a simple sense amplifier can be employed because the output signal only has one polarity; that is to say the output signal is either always plus or always minus.

The features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawing.

Examine the drawing wherein there is shown a core array 11 which represents a normal array of two rows by four columns by three bits. The first row of cores would be composed of cores 12 through 23 while the second row of cores would include the cores 24 through 35. In addition the same cores are divided into column configurations. The first column includes the cores 12, 13, 14, 33, 34, and 35. The second column of cores includes the cores 15, 16, 17, 30, 31, and 32. The third column of cores includes the cores 18, 19, 20, 27, 28 and 29. Finally, the fourth column of cores includes the cores 21, 22, 23, 24, 25 and 26.

Since there are three bits to a digit, it is apparent that if the system wants to select a digit, it simply selects the proper row driver and column driver and accordingly the proper digit (set of cores) is selected. For instance, if the system were instructed to select (for either a read or a write operation) the digit made up of the cores 12, 13, and 14 it would simply select the X1 row current driver 36 and the Y1 column current driver 37. It is of interest to note that the column line and the row line are arranged to lie parallel to one another and to have current passed therealong enter the face of the respective cores from the same side. Having once established that the row and column drive lines lie parallel to one another and enter the core from the same face (in the current film sense) the sense line disposed to lie orthogonal to the row and the column lines. In the particular embodiment shown the sense lines 38, 39 and 40 enter the faces of the core which are opposite from the faces of the cores into which the row and the column lines enter.

It is also apparent from examining the figure that the inhibit lines 41, 42, and 43 which are connected to the inhibit drivers 44, 45, and 46 are also arranged to lie orthogonally to the row and column lines and enter the faces of the cores which lie opposite from the faces that the row and column lines enter.

Consider that the system is directed to read the information in the cores 12, 13 and 14. Consider that the information in the cores 12, 13 and 14 is 1-0-1. In other words, consider that the cores 12 and 14 are magnetized in the direction to which there has been assigned the value of 1, while the core 13 is magnetized in the other magnetic state to which there has been assigned the value of 0. In accordance with the command to read the information from the cores 12, 13 and 14, current is passed from the X1 row current driver 36 along the line 47, as shown by the arrow 48 and in a like manner current is driven from the Y1 column current driver 37 along the line 49 as shown by the arrow 50.

The arrangement, accordingly, will be such that the flux in the cores 12 and 14 will lie in a direction which is opposite from the flux generated by the currents in 47 and 49. When the current is passed along the lines 47 and 49 the cores 12 and 14 will have a change in magnetic state, and this change in flux being linked by the respective lines 40 and 38 will generate a voltage in those sense lines. The voltage in the sense lines 40 and 38 will be respectively detected by sense amplifiers 51 and 52. Since the flux in the core 13 will be in the same direction as the flux generated by the current in lines 47 and 49 there will be no change in magnetic state of the core 13 and hence no voltage will be generated on line 39.

The current 48 will pass through the cores 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 and 23. Each of the cores through 23 will be partially switched and will generate a noise signal on the respective sense lines that pass therethrough. However, since this is a relatively small memory the amount of noise generated will not be sufficient to swamp out the valid signal or make the valid signal incapable of detection. Similarly, the current 50 will pass through the cores 13, 14 and 15, as well as the cores 33, 34, and 35. Each of the cores 33, 34 and 35 will alse generate a noise signal but as was discussed in connection with the other cores generating a noise signal, this noise will not affect the valid signal.

It is apparent that when the cores have had information read therefrom this information is destroyed and if it is to be used a second time it must be re-entered. The reentry of the information is accomplished by effecting the reverse of the readout with one additional innovation.

Assume that the same information is to be rewritten in cores 12, 13 and 14; and, accordingly, the X row current driver will draw current from the ground level 53 in accordance with the arrow 54, while the Y column current driver will draw current from the ground source 55 in accordance with the arrow 56. It becomes apparent that the X row current driver 36 and the Y column current driver 37 are bidirectional current drivers which are well known in the art. With the currents 54 and 56 passing through the cores 14, 13 and 12, each of these cores would be switched to represent a 1 value. However, it is not the intention of the system to record or rewrite 1-1-1, but rather 1-0-1, and hence the core 13 must have some additional consideration. The additional consideration to the core 13 is effected by having the inhibit driver 45 draw current from the ground level 57 in accordance with the arrow 58. The inhibit current is a half value current which bucks out, or nullifies, at least one of the half current values on either the line 47 or 49, and hence there is not sufi'icient flux generated to switch the core 13 from a reset or 0 condition. The core 13 remains as a O and the system has written 1-0-1 into the cores 12, 13 and 14.

The present core array can be expanded into many rows and columns simply by adding more segments of 3 by 4 cores each of which represents an additional row and simply running the column lines through the properly selected positions.

The advantages of using a fabrication arrangement such as shown in the drawing is that the cores can be simply threaded, in a manner similar to threading a set of beads, along the inhibit and sense lines. Thereafter a pair of row and column driver lines can be added by simply stitching the cores with these lines so that these lines lie orthogonally to the sense and inhibit lines. In other words a row wire can be threaded through one group of cores such as cores 12, 13 and 14, and from top to bottom through cores 15, 16 and 17. In the alternative, a loop stitch can be used with the wire passing first through 12, 13 and 14 and then through 17, 16 and 15.

In addition, the fact that the noise which is generated is ignored, or considered insignificant, enables the sense line to lie orthogonally to the row and column lines and hence the output signal always has the same polarity. Since the output signal always has the same polarity a relatively simple sense amplifier can be employed by comparison to a relatively complicated sense amplifier in the prior art systems which must be able to detect either a plus or a minus polarity output signal.

While the invention has been particularly shown and described with reference to a preferred embodiment it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A coincident current magnetizable core memory comprising in combination: a plurality of magnetizable cores arranged on a single plane according to N horizontal rows and M vertical columns wherein N is a multiple of the number of bits in a digit and M is a multiple of the number of digits in a word, said cores further arranged so that each core along a row is disposed at an angle which is substantially orthogonal to a core adjacent thereto along said row and wherein each of said cores located along a column is disposed substantially at the same angle as each other core along said column; said cores identified according to first and second groups, wherein each of said first groups has R columns therein where R is M divided by the number of digits in a word stored in said memory and wherein said second group includes the same number of columns that there are numbers of digits in a word; a plurality of first, second, third and fourth electrically conductive lines; each of said first electrically conductive lines threaded vertically through a different one of said first groups of columns of cores so that it passes from bottom to top for every other column in said last mentioned group and from top to bottom for each alternate column of said last mentioned group; each of said second electrically conductive lines threaded vertically through a different one of said second groups so that each of said second electrically conductive lines is threaded from top to bottom 5 6 for every other column and from bottom to top for each References Cited of the alternate columns of said second groups of columns UNITED STATES PATENTS of cores; each of said third electrically conductive lines associated with and threaded through a different row of 3212068 10/1965 v'lnal 340174 said magnetizable cores and adapted to be connected to 3,312,958 4/1967 ElsPman et a different inhibit signal driver; and each of said fourth 5 3,312,961 4/1967 Ralchman 340174 electrically conductive lines threaded horizontally through a dilferent row of said magnetizable cores and adapted to BERNARD KONICK Pnmary Exammer be connected to a difierent sense amplifier. GARY M. HOFFMAN, Assistant Examiner 

